The present invention relates in general to the field of integrated circuits and, more particularly, to the area of integrating power distribution between an integrated circuit chip and an interposer section from a wafer level interposer that are coupled together to form a chip assembly.
Modern electronic devices utilize semiconductor integrated circuits, commonly referred to as xe2x80x9cchips,xe2x80x9d which incorporate numerous electronic elements. These chips are typically manufactured in a wafer format, in which numerous similar devices, known as xe2x80x9cdiexe2x80x9d are constructed on a base made from a silicon ingot. Typical silicon wafers have an eight inch diameter (200 mm) with more recent silicon wafers having a twelve inch diameter (300 mm). Once manufactured, these chips are mounted on a substrate which physically support the chips and electrically interconnect the chips with other elements of the circuit. Such substrate may then be secured to an external circuit board or chassis for eventual incorporation into an electronic device.
Demand continues to grow for electronic devices that are smaller, faster, less expensive, more reliable, have a reduced thermal profile and contain more features. These requirements fuel the need for integrating more functionality into smaller form factor die. Several approaches have been attempted to achieve this desired high density integration. One approach is through the use of a system-on-a-chip (SOC). SOC devices typically integrate existing, discrete die into one aggregate die. It has been found, however, that the time it takes to design a SOC is typically longer than the time it takes to integrate a plurality of discrete die together. For example, if a SOC is designed to include a microprocessor, system memory and a controller chip, this design process is more complicated and takes more time as compared to integrating the components in discrete packages, in a flip chip module or in a multichip module. In addition, SOC development is hindered by product roadmap challenges. If compatible circuits are merged into one die, it becomes much more difficult to iterate the individual blocks. For example, if a CPU, a level 2 cache and a North Bridge core were all placed into one integrated die, and if some breakthrough technology was accomplished in the North Bridge core, this new North Bridge core could not simple replace the prior North Bridge core in the SOC, thereby preventing immediate release. Instead, the new design would have to be merged with the other parts forcing the new product release to occur in accordance with the overall product roadmap for the aggregate device. This process slows time to market, requires more management and more integration testing. Thus, these requirements alone may preclude the SOC approach.
In other cases, however, SOC is not even possible. For example, digital components, analog components and memory components can not be integrated into one die. Specifically, digital die are optimized for speed, with less regard for leakage currents and noise while a memory device, can not have high leakage current as it would drop bits and not function properly as a memory device. Likewise, the higher noise levels in digital circuits are not compatible with analog circuits, as analog circuits do not process incoming signals as a xe2x80x9c1xe2x80x9d or a xe2x80x9c0.xe2x80x9d
Another approach that has been attempted to achieve high density integration is to decrease the width and pitch of the interconnect etch and vias in the semiconductor die. For example, over the past few years, interconnect technology has moved from geometries in the tens of microns to the submicron realm. As such, increases in die density have been achieved. It has been found, however, that small decreases in geometry require the investment of significant capital for equipment, process engineering and design tools. In addition, it has been found that the producibility of die having these reduced interconnect geometries is lower than that of die with larger interconnect geometries. As such, die shrinks are not always feasible or practical.
Therefore, a need has arisen for improved high density integration of integrated circuits. A need has also arisen for such high density integration of integrated circuits that meets the requirement for time to market. A need has further arisen for such improved high density integration of integrated circuits while maintaining acceptable producibility levels.
The present invention disclosed herein provides for improved high density integration of integrated circuits through the use of a wafer-level interposer that is attached to a wafer prior to singulation such that some of the power distribution routing and interconnects typically integrated into each die are handled by the section of interposer attached to each die after singulation. The present invention achieves high density integration without the increases in time to market typically associated with SOC devices. In addition, the present invention achieves high density integration without the reduction in producibility typically associated with a die shrink. Specifically, by allowing a section of interposer to remain with the chip and handle some of the power distribution, die design can be simplified, a reduction in die density can be achieved, more functionality can be added to a die and die shrinks may be enabled.
The present invention disclosed herein comprises a chip assembly having an integrated circuit chip coupled to a wafer interposer section by electrically and mechanically connecting first and second sets of contact pads of the wafer interposer section with first and second sets of contact pads on the integrated circuit chip. The wafer interposer section has first and second supply voltage terminals that are electrically coupled to the first and second sets of contact pads of the wafer interposer section by first and second power distribution networks which allow for the integration of power distribution between the integrated circuit chip and the wafer interposer section.
More specifically, the wafer interposer section provides numerous points at which voltages, at various levels, may be provided to numerous contact pads on the integrated circuit chip. For example, the first supply voltage terminal, operating at a positive voltage, is electrically coupled to numerous contact pads using the first power distribution network. Likewise, the second supply voltage terminal, operating at ground, is electrically coupled to numerous contact pads using the second power distribution network. Thus, a large number of voltage supply paths may be created between the integrated circuit chip and the wafer interposer section which greatly reduce the complexity of power distribution within the integrated circuit chip. In fact, the integrated circuit chip in the chip assembly of the present invention utilizes numerous strategically positioned power distribution networks to distribute power within the integrated circuit chip in a highly efficient manner.
Generally speaking, each power distribution network of the integrated circuit chip is electrically coupled to one of the contact pads of the integrated circuit chip. Such power distribution networks may comprise a via and a power conductor which is typically disposed in a plane substantially perpendicular to the via. The power conductor may extend in one or more direction from the via depending upon the power distribution requirements. Alternatively, the power distribution network may be electrically coupled to two or more of the contact pads of the integrated circuit chip so long as each of the contact pads is at the same voltage potential. Such voltage potentials include positive voltages, negative voltages and ground.
The present invention also comprises a power distribution system for a chip assembly. The power distribution system includes first and second voltage supply terminals on one surface of a wafer interposer section. The first and second voltage supply terminals are electrically coupled to first and second power distribution networks disposed within the interposer section. A first set of contact pads on the other surface of the wafer interposer section are electrically coupled to the first power distribution network. Likewise, a second set of contact pads on that surface of the wafer interposer section are electrically coupled to the second power distribution network. The power distribution system is completed by electrically coupling a first set of contact pads on an integrated circuit chip to the first set of contact pads of the wafer interposer section and electrically coupling a second set of contact pads on the integrated circuit chip to the second set of contact pads of the wafer interposer section.
The method for distributing power to a chip assembly of the present invention involves, providing a first supply voltage to a first voltage supply terminal on a first surface of a wafer interposer section, providing a second supply voltage to a second voltage supply terminal on the first surface of the wafer interposer section, electrically coupling first and second power distribution networks disposed within the wafer interposer section to the first and second voltage supply terminals, electrically coupling a first set of contact pads on a second surface of the wafer interposer section to the first power distribution network, electrically coupling a second set of contact pads on the second surface of the wafer interposer section to the second power distribution network and electrically coupling first and second sets of contact pads on an integrated circuit chip to the first and second sets of contact pads on the second surface of the wafer interposer section.